Almost every grid-following inverter on the system synchronises through a synchronous reference frame phase-locked loop. The SRF-PLL takes the measured three-phase voltage, rotates it into the dq frame with its own estimated angle, and drives the q-axis voltage to zero with a PI loop filter. Linearised about the locked point it collapses to a textbook second-order system, which is why its two design numbers, bandwidth and damping, can be reasoned about on paper before anything is simulated.
This calculator works in both directions. In design mode you set a target closed-loop bandwidth or settling time together with a damping ratio and it returns the loop filter gains. In analysis mode you enter the gains you already have and it returns the bandwidth, damping, phase margin, overshoot and settling time. It also screens the resulting bandwidth against the short-circuit ratio at the connection point, because a fast PLL in a weak grid is one of the better documented ways to make a converter unstable.
SRF-PLL Tuning Calculator
Design or analyse a second-order PLL loop filter, then check bandwidth, damping and weak-grid margin
The small-signal model behind the numbers
Write the grid voltage angle as \(\theta_g\) and the PLL estimate as \(\hat{\theta}\). After the Park transform the q-axis voltage is \(v_q = V_g \sin(\theta_g-\hat{\theta})\). Near lock the sine linearises, so \(v_q \approx V_g\,(\theta_g-\hat{\theta})\). Dividing \(v_q\) by the measured amplitude \(V_g\) makes the phase detector gain exactly one. That normalisation is not cosmetic: without it the loop gain is proportional to the grid voltage, so the PLL slows down during a voltage sag and speeds up during a swell, precisely when its behaviour matters most.
The loop filter is a PI controller and the voltage-controlled oscillator is a pure integrator, so the open loop is
\[ L(s)=\left(k_p+\frac{k_i}{s}\right)\frac{1}{s}=\frac{k_p s+k_i}{s^{2}} \]
and closing the loop from grid phase to estimated phase gives a second-order transfer function with one zero:
\[ H(s)=\frac{L(s)}{1+L(s)}=\frac{k_p s+k_i}{s^{2}+k_p s+k_i},\qquad \omega_n=\sqrt{k_i},\qquad \zeta=\frac{k_p}{2\sqrt{k_i}} \]
Inverting those two definitions is the whole of design mode: \(k_p=2\zeta\omega_n\) and \(k_i=\omega_n^{2}\). The only remaining question is how to pick \(\omega_n\), and that is what the bandwidth or settling-time target does.
Bandwidth, and why the zero matters
The numerator zero at \(s=-k_i/k_p\) is often ignored, and it should not be. Setting \(|H(j\omega)|^{2}=1/2\) and solving for \(u=\omega^{2}\) gives a quadratic whose positive root is exact:
\[ \omega_{bw}=\omega_n\sqrt{\left(1+2\zeta^{2}\right)+\sqrt{\left(1+2\zeta^{2}\right)^{2}+1}} \]
At \(\zeta=0.707\) that factor is 2.058, so the closed-loop bandwidth is roughly twice the natural frequency, not the 1.27 you would get for a two-pole system with no zero. The same zero lifts the step response: a pure two-pole system at \(\zeta=0.707\) overshoots about 4.3 percent, while this loop overshoots about 20 percent. The tool integrates the closed loop with RK4 rather than quoting the textbook two-pole formula, so the overshoot and settling time it reports include the zero.
The open loop crosses unity gain where \(\omega^{4}=k_p^{2}\omega^{2}+k_i^{2}\), and the phase margin follows directly from the single zero:
\[ \omega_c=\sqrt{\frac{k_p^{2}+\sqrt{k_p^{4}+4k_i^{2}}}{2}},\qquad \mathrm{PM}=\arctan\!\left(\frac{k_p\,\omega_c}{k_i}\right) \]
Because the plant is a double integrator, the phase margin comes entirely from the PI zero. At \(\zeta=0.707\) it works out to about 65.5 degrees, and it is a monotonic function of damping alone: two designs with the same \(\zeta\) have the same phase margin regardless of how fast they are.
Steady-state tracking: what a type-2 loop does and does not do
The phase error transfer function is \(E(s)/\Theta_g(s)=s^{2}/(s^{2}+k_p s+k_i)\). Two zeros at the origin mean the loop tracks a phase step and a frequency step with zero steady-state phase error, which is the reason a PI loop filter is used at all rather than a plain proportional one. A frequency ramp is different. For \(\mathrm{d}\omega/\mathrm{d}t=R\) in rad/s the phase input is \(R/s^{3}\) and the final value theorem gives a constant lag:
\[ e_{ss}=\lim_{s\to 0}s\cdot\frac{R}{s^{3}}\cdot\frac{s^{2}}{s^{2}+k_p s+k_i}=\frac{R}{k_i} \]
This is the term that matters during a high RoCoF event. A slow PLL has a small \(k_i\) and therefore a large standing phase error while frequency is moving, and that error appears directly as an error in the dq frame the current controller works in.
Worked example
Take the default case: a 50 Hz grid, a target bandwidth of 25 Hz and \(\zeta=0.707\). The bandwidth relation gives \(\omega_n = 2\pi(25)/2.058 = 76.3\) rad/s, so \(k_i=\omega_n^{2}=5826\ \mathrm{s^{-2}}\) and \(k_p=2\zeta\omega_n=107.9\ \mathrm{s^{-1}}\). The gain crossover lands at 18.9 Hz with 65.5 degrees of phase margin. A phase step settles to within 2 percent in about 64 ms after overshooting 20.8 percent, and a 1 Hz/s frequency ramp leaves a standing lag of \(360/5826 = 0.062\) degrees.
Now press Load example, which is the same converter connected at SCR 1.6 with the bandwidth pulled back to 12 Hz and damping raised to 0.9. The gains drop to \(k_p=58.3\) and \(k_i=1048\), the loop is visibly slower, and the ramp lag grows by a factor of 5.6. That trade is the heart of PLL design: bandwidth buys you fast, accurate tracking during transients, and costs you margin against interaction with a weak grid.
How to read the classification
The chip combines two independent judgements. The damping test is uncontroversial: below about \(\zeta=0.5\) the phase step response is clearly oscillatory, and 0.7 to 1.0 is the range most design guidance settles on. The bandwidth test is a screening rule of thumb, not a stability boundary. It reflects published practice, in which PLL bandwidths of a few tens of hertz are common in strong grids and are reduced substantially as the short-circuit ratio falls, but it is deliberately not presented as a hard limit.
- Balanced design: damping in the working range and bandwidth at or below the screening value for the entered SCR. A reasonable starting point for a detailed study.
- Review this: either the damping is outside roughly 0.6 to 1.2, or the bandwidth is above the screening value for the entered SCR. Not a verdict of instability, a prompt to look harder.
- Review this closely: damping below about 0.4, or bandwidth well above the screening value for the entered SCR. This combination should not go forward on the strength of a second-order model. Confirm it with impedance-based analysis or an EMT study.
Nothing in this tool can tell you where the true stability boundary is. The PLL is only one loop in a converter that also has a current controller, an outer power or voltage loop, and a grid impedance that all interact. The recognised methods for finding the boundary are impedance-based or eigenvalue analysis of the coupled system and electromagnetic transient simulation. Use the classification to decide what deserves that effort, not to replace it.
Working in per-unit?
The free Per-Unit System Cheat Sheet covers base selection and change of base, including the voltage base this calculator normalises the phase detector against, on one printable page.
Frequently asked questions
Why does my overshoot not match the textbook second-order formula?
Because this loop is not a pure two-pole system. The PI loop filter puts a zero at \(s=-k_i/k_p\) in the closed-loop numerator, and that zero adds a derivative term to the step response. At \(\zeta=0.707\) the two-pole formula predicts about 4.3 percent overshoot while the actual response overshoots about 20 percent. The calculator integrates the real closed loop numerically, so its overshoot and settling time include the zero.
Should the phase detector be normalised by the voltage amplitude?
In almost all cases yes. The linearised detector gain is the grid voltage amplitude, so without normalisation the loop gain, the bandwidth and the damping all move with the terminal voltage. Dividing the q-axis voltage by the measured amplitude removes that dependence, which is why the loop keeps its designed dynamics during a fault. Untick the normalisation box in the tool and change the voltage to see how far the effective gains drift.
What bandwidth should I use in a weak grid?
There is no single number, and any tool that gives you one is overselling. The direction of travel is well established: as the short-circuit ratio falls, reducing PLL bandwidth is the standard first mitigation for PLL-driven small-signal instability, and strong-grid bandwidths of a few tens of hertz are commonly reduced substantially for weak connections. The value at which your specific converter becomes unstable depends on the current controller, the outer loops and the network impedance together, and has to come from an impedance scan or an EMT study.
Does this model cover unbalance and harmonics?
No. It assumes a balanced fundamental-frequency input. Under unbalance the negative-sequence component appears as a second-harmonic ripple on the q-axis voltage, which a plain SRF-PLL passes straight through to the frequency estimate. The usual fixes are a prefilter such as a DSOGI or a decoupled network, or an in-loop notch at twice the fundamental. Any of those adds dynamics that this second-order model does not represent.
Is settling time or bandwidth the better design target?
Bandwidth, if you care about interaction with the grid or with other control loops, because that is the quantity the frequency-domain arguments are written in. Settling time is the more intuitive target when the requirement is stated as a ride-through or recovery time. The tool maps settling time to natural frequency with the usual convention \(t_s \approx 4/(\zeta\omega_n)\) and then reports the settling time actually obtained from the integrated response, which differs slightly because of the numerator zero.
Related reading
- All EE Power School calculators: the full set of interactive power system tools.
- SCR Calculator: work out the short-circuit ratio this tool screens the bandwidth against.
- SRF-PLL Design: Synchronizing an Inverter to the Grid: the structure, the tuning, and the DSOGI variants in full.
- PLL Synchronization Instability in Weak Grids: what actually goes wrong when a fast PLL meets a low SCR.
- Inside a Grid-Following Inverter: The Control Loops: where the PLL sits relative to the current and outer loops.
- Two-Bus Load Flow Calculator: the companion tool for steady-state voltage stability.
References
- R. Teodorescu, M. Liserre and P. Rodríguez, Grid Converters for Photovoltaic and Wind Power Systems, Wiley-IEEE Press, 2011, chapter 4 (grid synchronisation).
- S.-K. Chung, “A phase tracking system for three phase utility interface inverters,” IEEE Transactions on Power Electronics, vol. 15, no. 3, pp. 431–438, 2000.
- D. Dong, B. Wen, D. Boroyevich, P. Mattavelli and Y. Xue, “Analysis of phase-locked loop low-frequency stability in three-phase grid-connected power converters considering impedance interactions,” IEEE Transactions on Industrial Electronics, vol. 62, no. 1, pp. 310–321, 2015.
- J. Sun, “Impedance-based stability criterion for grid-connected inverters,” IEEE Transactions on Power Electronics, vol. 26, no. 11, pp. 3075–3078, 2011.
- K. Ogata, Modern Control Engineering, 5th ed., Prentice Hall, 2010, chapter 5 (second-order transient response).