SRF-PLL Design: Synchronizing an Inverter to the Grid
Before a grid-following inverter can inject a single ampere correctly, it has to answer one question continuously: what is the grid’s angle right now? Get it wrong by a few degrees and your active and reactive power split is wrong; get it badly wrong and the inverter fights the grid. The synchronous reference frame phase-locked loop (SRF-PLL) is the standard answer, and SRF-PLL design is one of those small components that quietly decides whether a converter is stable or not.
This post is a design-level walk through the SRF-PLL: how it is built, how to model it as a second-order loop and tune its two gains from a damping ratio and a natural frequency, the bandwidth trade-off that has no free lunch, and why the very same fast PLL that tracks beautifully on a strong grid can destabilize a weak one. We will work the tuning with real numbers and connect it to the weak-grid instability that bites real projects.
What the PLL Is Actually For
Everything in grid-following control lives in the dq frame, and the dq frame needs an angle, the estimate of where the grid voltage vector is pointing. That angle feeds every Park transform in the converter. The PLL is the loop that produces it, tracking the grid’s phase and frequency in real time so the controller stays locked to the grid even as frequency drifts.
A good PLL is invisible: it hands the current loops a clean angle and you forget it exists. A poorly designed one is the opposite, it lets noise and unbalance leak into the angle, lags during transients, or, worst of all, turns into the source of an instability. That is why SRF-PLL design deserves real attention rather than a copied set of gains. The angle is the foundation everything else is built on, and a shaky foundation shows up everywhere.
The SRF-PLL Structure
The SRF-PLL is elegantly simple. It uses the Park transform itself as the phase detector. The trick: transform the grid voltage into dq using the PLL’s own estimated angle, and watch the q-axis component. When the estimated angle matches the real angle, the d-axis lines up with the voltage and \( v_q \) is zero. Any angle error shows up as a nonzero \( v_q \). So the loop simply drives \( v_q \) to zero:
- Park-transform the measured voltage using the estimated angle to get \( v_q \).
- Feed \( v_q \) into a PI loop filter, whose output is the estimated frequency \( \hat{\omega} \).
- Integrate \( \hat{\omega} \) to get the estimated angle \( \hat{\theta} \), and feed it back into the Park transform.
For small errors the phase detector is nearly linear, \( v_q \approx V\,\Delta\theta \), where \( V \) is the voltage amplitude. The diagram shows the full loop. That closed chain, detect angle error, integrate to frequency, integrate to angle, is the whole of the SRF-PLL, and the rest of SRF-PLL design is choosing the PI gains well.
SRF-PLL Design: Tuning the Second-Order Loop
Linearised around lock, the SRF-PLL is a textbook second-order system. With the PI loop filter and the integrator-to-angle, the closed-loop response from real angle to estimated angle is:
\[ H(s) = \frac{2\zeta\omega_n s + \omega_n^2}{s^2 + 2\zeta\omega_n s + \omega_n^2} \]
which means the two PI gains map directly onto a chosen damping ratio \( \zeta \) and natural frequency \( \omega_n \):
\[ K_p = \frac{2\zeta\omega_n}{V}, \qquad K_i = \frac{\omega_n^2}{V} \]
The voltage amplitude \( V \) appears because it is the phase-detector gain; many implementations normalise \( v_q \) by \( V \) (or work in per unit with \( V = 1 \)), which drops it out. The standard damping choice is \( \zeta = 1/\sqrt{2} \approx 0.707 \), the classic best trade-off between speed and overshoot. Work an example: pick \( \zeta = 0.707 \) and \( \omega_n = 2\pi(30) = 188.5 \) rad/s (a ~30 Hz loop, a common real-grid choice). In per unit:
\[ K_p = 2(0.707)(188.5) = 266, \qquad K_i = 188.5^2 = 35530 \]
The settling time follows from the second-order form, \( t_s \approx 4/(\zeta\omega_n) = 4/133 \approx 30 \) ms, about 1.5 line cycles at 50 Hz. That is SRF-PLL design in three numbers: pick \( \zeta \), pick \( \omega_n \), read off \( K_p \) and \( K_i \).
The Bandwidth Trade-Off With No Free Lunch
The natural frequency \( \omega_n \) sets the PLL bandwidth, and choosing it is the heart of SRF-PLL design because it pulls in two opposite directions. A high bandwidth PLL tracks fast: it locks quickly after a phase jump, follows frequency ramps tightly, and recovers fast from faults. A low bandwidth PLL is calm: it rejects noise, harmonics and unbalance because it averages over them, but it is sluggish to track real changes.
You cannot have both. Push the bandwidth up for fast tracking and you let more \( 2\omega \) ripple from unbalance and more measurement noise straight into your angle. Pull it down for clean rejection and the PLL lags during transients. The lock chart shows a fast and a slow PLL responding to a phase step: the fast one snaps to zero error with a little overshoot, the slow one eases in without overshoot but takes far longer. The trade-off chart makes the tension explicit, tracking speed and disturbance rejection cross as bandwidth rises, and a common compromise lands around 30 to 50 Hz. There is no universally right answer, only the right answer for your grid.
Handling Unbalance: DSOGI and DDSRF
The basic SRF-PLL has a known weakness we met in the dq transformation: under voltage unbalance, the negative-sequence component injects a double-frequency (\( 2\omega \)) ripple into \( v_q \), which the PLL then tracks as angle wobble. Lowering the bandwidth helps but makes the PLL slow. The better answer is to remove the negative sequence before it reaches the loop, and two structures dominate.
The DSOGI-PLL (dual second-order generalised integrator) uses a pair of adaptive quadrature-signal generators in the stationary frame to extract the positive-sequence fundamental, so the PLL only ever sees a clean balanced signal. The DDSRF-PLL (decoupled double synchronous reference frame) runs two frames, one spinning each way, with a decoupling network that cancels the \( 2\omega \) cross-coupling between them. Both let you keep a reasonably fast loop while staying immune to unbalance, which is why serious SRF-PLL design for real grids almost always graduates to one of them. They are more complex, but they break the bandwidth-versus-unbalance compromise that limits the plain SRF-PLL.
Why a Fast PLL Can Wreck a Weak Grid
Here is the consequence that turns SRF-PLL design from a tuning exercise into a stability problem. On a strong grid, the PLL measures a voltage that the inverter barely affects, so the loop is benign. On a weak grid (low short-circuit ratio), the inverter’s own current noticeably moves the local voltage, and now there is a feedback path the PLL did not bargain for: the PLL adjusts the current, the current moves the voltage, the voltage moves \( v_q \), the PLL adjusts again.
If the PLL is fast, that feedback can become regenerative, the loop effectively injects negative damping, and the converter oscillates or goes unstable, even though every component is fine in isolation. This is one of the central mechanisms behind weak-grid instability in grid-following inverters. The practical takeaway is sharp: in a weak grid you often have to slow the PLL down, trading tracking speed for stability, or move to grid-forming control that does not rely on a PLL at all. SRF-PLL design and grid strength are not separate topics, the right bandwidth depends on the short-circuit ratio you are connecting into.
Conclusion
The SRF-PLL is deceptively small: a Park transform, a PI controller, and an integrator. Yet SRF-PLL design carries more weight than its size suggests, because the angle it produces is the reference frame for the entire converter, and the bandwidth you choose for it is a direct bet on the grid you are connecting to.
The discipline is the same as the rest of control design: model it (a second-order loop), tune it from a damping ratio and a natural frequency, and then respect the trade-off. Fast for clean grids, slower for weak ones, and a DSOGI or DDSRF front end when unbalance is in play. And when you find yourself forced to slow the PLL so much that it can no longer do its job, that is the grid telling you it is time to consider grid-forming control. The PLL is where grid-following inverters meet their limits, which makes getting it right one of the highest-leverage skills in inverter engineering.
Key takeaways
- The SRF-PLL estimates the grid angle that every Park transform in a grid-following inverter depends on.
- It uses the Park transform as a phase detector: drive the q-axis voltage to zero with a PI loop filter, integrate its output to the angle, and feed back.
- Linearised it is a second-order loop, so Kp = 2 zeta omega_n / V and Ki = omega_n^2 / V; zeta = 0.707 is the standard damping choice.
- Worked tuning: zeta = 0.707 and a 30 Hz loop (omega_n = 188.5) give Kp = 266, Ki = 35530, and a settling time of about 30 ms (1.5 cycles at 50 Hz).
- Bandwidth is a trade-off: fast tracks well but lets in noise and 2 omega unbalance ripple; slow rejects disturbances but lags. A common compromise is 30 to 50 Hz.
- DSOGI-PLL and DDSRF-PLL reject unbalance so you can keep a fast loop, and on weak grids a fast PLL can inject negative damping and destabilize the converter.
Frequently Asked Questions
What is an SRF-PLL?
A synchronous reference frame phase-locked loop estimates the grid voltage angle and frequency for a grid-connected inverter. It Park-transforms the voltage using its own estimated angle, drives the resulting q-axis voltage to zero with a PI loop filter to get the estimated frequency, and integrates that to the angle, which feeds every dq transform in the controller.
How do you tune the SRF-PLL gains?
Model it as a second-order loop and pick a damping ratio and natural frequency. Then Kp = 2 zeta omega_n / V and Ki = omega_n squared / V, where V is the voltage amplitude. With zeta = 0.707 and a 30 Hz loop (omega_n = 188.5 rad/s) in per unit, Kp is about 266 and Ki about 35530, giving roughly a 30 ms settling time.
What is the SRF-PLL bandwidth trade-off?
A higher-bandwidth PLL tracks phase and frequency changes faster but lets in more measurement noise and more double-frequency ripple from unbalance. A lower-bandwidth PLL rejects those disturbances but responds slowly to real changes. A common compromise is a bandwidth around 30 to 50 Hz, adjusted for the grid.
Why does a fast PLL cause problems in a weak grid?
In a weak grid the inverter's own current noticeably moves the local voltage, creating a feedback path through the PLL. A fast PLL can make this feedback regenerative, effectively injecting negative damping, so the converter oscillates or goes unstable. The fix is often to slow the PLL down or move to grid-forming control, which needs no PLL.
Related reading
- Power system simulation using PSS/E
- Single line diagram of a power system
- The future of the electric grid with renewable and green energy
- Electrical Engineering Formula Cheat Sheet (power systems quick reference)
References
- S.-K. Chung – A phase tracking system for three-phase utility interface inverters (IEEE)
- Golestan, Guerrero & Vasquez – Three-Phase PLLs: A Review of Recent Advances (open access)
- Rodriguez et al. – Positive-sequence detector for grid synchronization (DSOGI, IEEE)
- imperix – Synchronous Reference Frame PLL implementation note
